In a MOS transistor of a 45-nm node or later generation, impurity distribution in impurity diffusion regions, especially in ultrashallow junction (extension) regions of source-drain regions extending under the gate electrode affects performance of the MOS transistor, such as the short channel effect thereof.
Here, the later node generation requires shallower ultrashallow junctions. However, the conventional processing method of forming ultrashallow junctions by firstly implanting impurity ions at a low acceleration voltage, and activating the implanted ions by low-temperature annealing has disadvantages such as variation in processing qualities, and these disadvantages causes a problem of making it difficult to accurately control the depth of ultrashallow junctions as required in various node generations.
Meanwhile, there has been known a semiconductor device using a silicon substrate that has a hybrid plane orientation for improving performance of a CMOS transistor.
H. Yin et al., “Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS,” IE DM Tech. Dig., pp. 75-78, 2006 (hereinafter, referred to as Non-patent Document 1) discloses a semiconductor device utilizing the principle that the electron mobility is largest on the (100) plane while the hole mobility is largest on the (110) plane. The semiconductor device uses a silicon substrate having a first region whose plane orientation is (100) and a second region whose plane orientation is (110), and an n-type MOS transistor is formed in the first region while a p-type MOS transistor is formed in the second region.
This structure improves the current drive capability of the p-type MOS transistor, and thus provides a high-performance CMOS transistor.
Here, in the semiconductor device disclosed in Non-patent Document 1, a channel region, extension regions and source-drain regions are formed in a single plane-orientation region of each of the n-type MOS transistor and the p-type MOS transistor, namely, the first region in the n-type MOS transistor or the second region in the p-type MOS transistor. Thus, the semiconductor device disclosed in Non-patent Document 1 may have the problem of difficulty in controlling the depth of ultrashallow junctions, as in conventional semiconductor devices.